Quick Detail:
The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on
advanced CMOS technology
Description:
Altera EP1810 devices offer LSI density, TTL-equivalent speed, and lowpower consumption. EP1810 devices have 48 macrocells, 16 dedicated input pins, and 48 I/O pins (see Figure 16). EP1810 devices are divided into four quadrants, each containing 12 macrocells. Of the 12 macrocells in each quadrant, 8 have quadrant feedback and are “local” macrocells (see “Feedback Select” on page 749 of this data sheet for more information). The remaining 4 macrocells in the quadrant are “global” macrocells. Both local and global macrocells can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of the feedbacks from the global macrocells.
EP1810 devices also have four dedicated inputs (one in each quadrant) that can be used as quadrant clock inputs. If the dedicated input is used as a clock pin, the input feeds the clock input of all registers in that particular quadrant.
Applications:
â– Complete device family with logic densities of 300 to 900 usable gates
â– Device erasure and reprogramming with non-volatile EPROM configuration elements
â– Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz
â– 24 to 68 pins available in dual in-line package (DIP), plastic J-lead chip carrier (PLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages
â– Programmable security bit for protection of proprietary designs
â– 100% generically tested to provide 100% programming yield
â– Programmable registers providing D, T, JK, and SR flipflops with individual clear and clock controls
â– Software design support featuring the Altera® MAX+PLUS® II development system on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000 workstations, and third-party development systems
â– Programming support with Altera’s Master Programming Unit
(MPU); programming hardware from Data I/O, BP Microsystems, and other third-party programming vendors
â– High-performance, 48-macrocell Classic EPLD
– Combinatorial speeds with t
PD as fast as 20 ns
– Counter frequencies of up to 50 MHz
– Pipelined data rates of up to 62.5 MHz
â– Programmable I/O architecture with up to 64 inputs or 48 outputs
â– Programmable clock option for independent clocking of all registers
â– Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
â– Available in the following packages (see Figure 15)
– 68-pin ceramic pin-grid array (PGA)
– 68-pin plastic J-lead chip carrier (PLCC)
Specifications:
|
part no. |
EP1810 |
|
Manufacturer |
Altera Corporation |
|
supply ability |
10000 |
|
datecode |
10+ |
|
package |
68pin-PLCC |
|
remark |
new and original stock |
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