AM29F400BB-45ED - Advanced Micro Devices - 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-on



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4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory





The Am29F400B is a 4 Mbit, 5.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words.

The device is offered in 44-pin SO and 48-pin TSOP packages. The device is also available in Known Good Die (KGD) form. For more information, refer to publication number 21258. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed insystem with the standard system 5.0 volt VCC supply. A 12.0V VPP is not required for write or erase operations. The device can also be programmed in standard EPROM programmers.

This device is manufactured using AMD’s 0.32 µm process technology, and offers all the features and benefits of the Am29F400, which was manufactured using 0.5 µm process technology.

The standard device offers access times of 45, 50, 55,70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6/DQ2 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.





â–  Single power supply operation

— 5.0 volt-only operation for read, erase, and program operations

— Minimizes system level requirements

â–  Manufactured on 0.32 µm process technology

— Compatible with 0.5 µm Am29F400 device

â–  High performance

— Access times as fast as 45 ns

â–  Low power consumption (typical values at 5 MHz)

— 1 µA standby mode current

— 20 mA read current (byte mode)

— 28 mA read current (word mode)

— 30 mA program/erase current

â–  Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword sectors (word mode)

— Supports full chip erase

— Sector Protection features:

A hardware method of locking a sector to prevent any program or erase operations within that sector

Sectors can be locked via programming equipment

Temporary Sector Unprotect feature allows code changes in previously locked sectors

â–  Top or bottom boot block configurations available

â–  Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors

— Embedded Program algorithm automatically writes and verifies data at specified addresses

â–  Minimum 1,000,000 program/erase cycles per sector guaranteed

â–  20-year data retention at 125°C

— Reliable operation for the life of the system

â–  Package option

— 48-pin TSOP

— 44-pin SO

— Known Good Die (KGD)

(see publication number 21258)

â–  Compatibility with JEDEC standards

— Pinout and software compatible with singlepower-supply Flash

— Superior inadvertent write protection

â–  Data# Polling and toggle bits

— Provides a software method of detecting program or erase operation completion

â–  Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting program or erase cycle completion

â–  Erase Suspend/Erase Resume

— Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation

â–  Hardware reset pin (RESET#)

— Hardware method to reset the device to reading array data





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